The present invention relates to a pattern inspection machine for inspecting the defects of an object and, more particularly, to a pattern data generating apparatus used for inspecting defects in a very small pattern in a photomask or wafer used to manufacture semiconductor devices or an apparatus for inspecting the defects of a liquid crystal substrate, and a pattern inspection machine using the pattern data generating apparatus.
One of the important causes which reduces the yield in the manufacture of large scale integrated circuits (LSIs) is a defect in a photomask used in manufacturing devices according to photo lithographic technology. In recent years, the size of a pattern formed along with the development of LSIs is reduced, and accordingly the size of the pattern to be detected as the defect is greatly reduced. High precision is required to detect the defect of the pattern. As an example of a configuration method for a machine for inspecting such a defect, there is available an inspection machine for detecting the defect of a pattern by comparing pattern design data used to form the pattern with actual measurement data. This machine requires a data generating circuit for generating the pattern design data used in forming the pattern and sending the generated data to a comparison circuit. A conventional data generating circuit performs so-called binary bit pattern generation. In the binary bit pattern generation, design data are developed into patterns one by one in accordance with a predetermined hierarchical structure. In accordance with the shape and size of a pattern, a pattern is expressed by the presence/absence of bits, i.e., "1" and "0" in the squares constituting a pattern having a predetermined size as a unit.
In this binary bit pattern generation, the inspection machine preferably matches the size of a grid of a pattern which is determined as one of operation parameters with a design grid size intended in preparing design data by a pattern designer due to the following reason. When these sizes are different from each other, for example, the edge portion of a pattern has an error at a maximum of .+-.1 pixel in the grid size of the bit pattern of the machine. The inspection machine tends to erroneously detect a shift in edge position. When a defect determination threshold value becomes less strict to prevent this erroneous detection, a defect to be detected may be missed.
Recent demand has arisen for reducing the size of a design pattern. That is, the design grid size must be further reduced. An inspection machine as a target of the present invention is of a database comparison type in which measurement data is compared with design data used to obtain the target measurement data. The generation rate of the pattern data greatly depends on the speed of the inspection machine. In the conventional binary bit generation, since the grid size of a bit pattern is determined depending on the grid size of the design data, a decrease in grid size requires a larger number of bits in bit generation of patterns having the same size. Therefore, the inspection machine must comprise a high-speed data processing circuit if the processing time in units of patterns is kept unchanged.
Similarly, when the volume of bit pattern data increases, the size of a circuit portion for filtering the bit pattern data must be increased. This filtering process is a process for acquiring the optical image of a target inspection pattern and, particularly, a process for simulating blur caused by the characteristics of an optical system, a sensor, and the like. In the conventional inspection machine, the blur is obtained by convoluting a point spread function on the order of about 10.times.10 pixels of bit-developed two-dimensional bit pattern data. When the bit pattern size of design data is reduced without changing an observation region size, the matrix arrangement of 10.times.10 pixels must be increased.
In pattern generation, data is generated into "1" or "0" depending on whether a pattern portion is present in a pattern grid. The squares of the bit pattern are formed in a checkerboard pattern by lines along the X- and Y-axes. No problem occurs when a pattern is constituted by only line segments along the X- and Y-axes. If a pattern has an inclined line, the inclined line crosses a square. In this case, this square should take a value of "0.5", strictly speaking. It is impossible to take such a value in binary development. The value of "0.5" is chopped to "0" or rounded up to "1". In either case, when design data having an inclined line is generated, some errors are included in the generation itself in a scheme of counting "1"s and "0"s. This problem can be solved by Jpn. Pat. Appln. KOKAI Publication No. 1-305344 in which a rectangular equilateral triangle is used as a unit area. In this case, however, a pattern is formed using a larger number of bits, a long processing time is required, and therefore this method is not practical. If pattern data can be generated not into "1" and "0", but into multivalue gray scale data, a more accurate result can be sent to a subsequent comparison circuit at high speed.
As previously described, when the design grid size is reduced, the bit generation circuit and the filter circuit which process the design data must process a large volume of data at high speed. The conventional system for filtering the binary bit pattern data has no room for improvement.
It is, therefore, an object of the present invention to provide a pattern data generating apparatus which can increase an apparent circuit operation speed by using a multivalue bit generation circuit and can improve the precision in terms of an improvement of an error of a conventional circuit which occurs in processing a portion containing inclined line or lines.